The anticipated variation in silicon processing and the range of environmental conditions must be considered when designing an integrated circuit to guarantee that the circuit meets the appropriate performance requirements. The variation in silicon processing and environmental conditions can cause significant circuit performance changes. As a result, compromises must often be made when designing a circuit to guarantee that the circuit is robust even in the presence of all silicon process and environmental effects. For example, the size of a CMOS buffer must be chosen larger than the size required for typical device performance in older to meet performance requirements under a silicon process and environment that produces “slow” devices
When a circuit is designed to meet all requirements in the presence of the full amount of silicon process and environmental conditions, the overall circuit performance is generally compromised. Specifically, a circuit designed under a set of “typical” process conditions must be sized greater than necessary under “typical” processing conditions to meet performance requirements under a set of “slow” process conditions. Supply currents under a “fast” silicon process case are much greater than required and, as a result, signal and power supply trace widths must be increased significantly to reduce the reliability risk of electromigration.
A number of techniques have been proposed or suggested for compensating for process variation and leakage current. For example, the impact of process variation is often reduced by designing a circuit such that the circuit is capable of meeting performance requirements over the entire range of silicon process and environmental conditions. Other techniques employ statistical device models that gauge the probability of a circuit parameter reaching an undesired level. With such statistical models, the “effective” silicon process variation is reduced to a low probability level. The “corner” cases, however are not eliminated
More recently, circuit techniques such as transistor-stacking, the use of multiple threshold devices, applying a body bias to devices subject to high leakage currents or forcing unused circuits in a device to a low leakage state have been employed to minimize device leakage current. Such techniques, however, either require new circuit design topologies not available in many common libraries, add silicon processing steps to allow for multiple CMOS device thresholds or require control techniques to adjust the body voltage of devices. Thus, the design time, circuit area, and cost may all be increased.
A need therefore exists for methods and apparatus for compensating for the impact of silicon process variation. A further need exists for methods and apparatus that compensate for silicon process variation while also reducing device leakage current and maximum device power dissipation